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cy7c68003 mobl-usb? tx2ul usb 2.0 ulpi transceiver cypress semiconductor corporation ?? 198 champion court ?? san jose , ca 95134-1709 ?? 408-943-2600 document number: 001-15775 rev. *i revised september 22, 2010 features the cypress mobl-usb? tx2ul is a low voltage high speed (hs) usb 2.0 utmi+ low pin interface (ulpi) transceiver. the tx2ul is specifically designed for mobile handset applications by offering tiny package options and low power consumption. usb 2.0 full speed and high speed compliant transceiver multi range (1.8v to 3.3v) i/o voltages fully compliant ulpi link interface 8-bit sdr ulpi data path utmi+ level 0 support support usb device mode only integrated oscillator integrated phase locked loop (pll ) ? 13, 19.2, 24, or 26 mhz reference integrated usb pu ll up and termination resistors 3.0v to 5.775v vbatt input chip select pin single ended device reset input uart pass through mode esd compliance: ? jesd22-a114d 8 kv contact human body model (hbm) for dp, dm, and vss pins ? iec61000 - 4-2 8 kv contact discharge ? iec61000 - 4-2 15 kv air discharge support for industrial temperature range: (-40 c to 85 c) low power consumption for mobile applications: ? 5 ua nominal sleep mode ? 30 ma nominal active hs transfer small package for mobile applications: ? 2.14 x 1.76 mm 20-pin wlcsp 0.4 mm pitch ? 4 x 4 mm 24-pin qfn applications mobile phones pdas portable media players (pmps) dtv applications portable gps units tx2ul ulpi block xosc ulpi wrapper utmi+ level0 data[7:0] clock dir stp nxt xi xo vbatt 13/19.2/ 24/26 mhz reset_n dp dm io control/ data logic operational mode tracking interrupt tx/rx core registers block global control block reset / clock / power / misc. control por pll 1.8v bandgap usb fs/hs phy cs_n 3.3v regulator block (3.0 ? 5.775v) vcc (1.8v) rxd txd tx2ul block diagram [+] feedback
cy7c68003 document number: 001-15775 rev. *i page 2 of 27 contents features............................................................................. 1 tx2ul block diagram ...................................................... 1 applications ...................................................................... 1 contents ............................................................................ 2 functional overview ........................................................ 3 utmi+ low pin interface (ulpi) ................................. 3 oscillator (osc) ........ .............. .............. .............. ........ 3 phase locked loop (pll)........................................... 3 power on reset (por)............................................... 3 reset (reset_n) ........ .............. .............. .............. ..... 3 dp and dm pins .......................................................... 3 chip select (cs_n) ..................................................... 3 usb2 transceiver macrocell interface (utmi+).......... 3 global control ............................................................. 3 full speed and high speed usb transceivers (fs/hs) .................................................. 3 usb pull up and intr dete ct, termination resistors (pull up/term)............................................................ 3 uart pass through mode ......................................... 3 clocking....................................................................... 4 power domains ........................................................... 4 operation modes......................................................... 5 vid and pid ................................................................ 6 pinouts .............................................................................. 7 synchronous operation modes ...................................... 9 ulpi transmit command byte (tx cmd) .................. 9 ulpi receive command byte (rx cmd) ................... 9 usb data transmit (nopid)... .................................. 10 usb data transmit (pid) ..... ..................................... 11 usb packet receive ............... .................................. 11 immediate register read and write ......................... 12 immediate register read and write aborted by usb receive .............................................................. 13 back to back immediate register read and write and usb receive ............................................................. 14 configuration mode........................................................ 16 configuration mode in 20-pin csp package ............. 16 configuration mode in 24-p in qfn package ............. 16 power on reset (por)............................................. 16 register ..................................................................... 16 register map ............................................................. 16 immediate register set............................................. 17 function control regi ster.......................................... 17 interface control register ......................................... 18 debug register ........ .............. .............. .............. ....... 18 scratch register........................................................ 18 carkit control register .............................................. 18 drive strength and slew rate configuration register ............................................... 19 usb interface control register ................................. 19 absolute maximum ratings .......................................... 20 operating conditions..................................................... 20 dc characteristics ......................................................... 21 ac characteristics ......................................................... 21 ordering information...................................................... 24 package diagram............................................................ 24 document history page ................................................. 26 sales, solutions, and legal information ...................... 27 worldwide sales and design supp ort............. .......... 27 products .................................................................... 27 psoc solutions ......................................................... 27 [+] feedback
cy7c68003 document number: 001-15775 rev. *i page 3 of 27 functional overview utmi+ low pin interface (ulpi) this block conforms to the ulpi specification. it supports the 8-bit wide sdr data path. the primary i/os of this block support multi-range lvcmos signaling from 1.8v to 3.3v (5%). the level used is automatically se lected by the voltage applied to v ccio and is set at any voltage between 1.8v and 3.3v. oscillator (osc) this block meets the requirements of both the on-chip pll and the usb-if requirements for clock parameters. it is a fundamental mode parallel reson ant oscillator with a maximum esr of 60 . it supports the following: integrated crystal oscillator ? 13 , 19.2, 24, or 26 mhz crystal 13, 19.2, 24, or 26 mhz lvcmos single ended input clock on xi phase locked loop (pll) the pll meets all clock stability requirements imposed by this device and the usb standard. it supports all requirements to make the device compliant to the usb 2.0 specifications. it also has a fractional multiplier that enables it to supply the correct frequency to the device when it is presented with a 13, 19.2, 24, or 26 mhz reference clock. power on reset (por) this block provides a por signal (internal) based on the input supply. an internal por is generated when vcc input rises above vpor(trip). reset (reset_n) the three major functions of reset_n pin are as follows: reset tx2ul place tx2ul into sleep mode place tx2ul into configuration mode when the reset_n pin is asserted (low) for tstate (tstate is specified in table 21 on page 21 ), the tx2ul enters either sleep mode or configuration mode depending on the cs_n state. when reset_n is asserted while cs_n is asserted, tx2ul enters sleep mode. when reset_n is asserted for tstate while cs_n is deasserted, tx2u l enters configuration mode. in these modes, all the pins in the ulpi interface are tristated. if the reset_n pin is not used, it must be pulled high. for information about different modes of configuration, see table 5 on page 5 . dp and dm pins the dp and dm pins are the differential pins for the usb. they must be connected to the corresponding dp and dm pins of the usb receptacle. chip select (cs_n) this signal pin is available only in 24-pin qfn package. the two major functions of cs_n are as follows: tristate the ulpi bus output pins associate with reset_n to pl ace tx2ul in the sleep mode when the cs_n pin is deasserted (high), all the pins in the ulpi interface are tristated. usb2 transceiver macrocell interface (utmi+) this block conforms to the utmi+ level 0 standard. it performs all the utmi to usb translation. global control this block is the digital control logic that ties the blocks of the device together. its functions include pull up control, over current protect control, and more. full speed and high speed usb transceivers (fs/hs) the fs and hs transceivers comply fully with the usb 2.0 specifications. usb pull up and intr detect, termination resistors (pull up/term) these blocks contain the usb pull up and termination resistors as specified by the usb 2.0 specification. uart pass through mode tx2ul supports carkit uart pass through mode. when the carkit mode bit in the interface control register is set, it enables the link to communicate through the dp/dm to a remote system using uart signaling. by default, the clock is powered down when the tx2ul enters carkit mode. entering and exiting the carkit mode is identical to the serial mode. ta b l e 1 , table 2, and figure 1 show the uart signal mapping between the dp/dm and data[1:0] at ulpi interface. figure 1. uart signal mapping in pass through mode table 1. uart signal ma pping at ulpi interface signal maps to direction description txd data[0] in uart txd signal routed to dm pin rxd data[1] out uart rxd signal routed to dp pin reserved data[7:2] - reserved table 2. uart signal mapping at usb interface signal maps to direction description txd dm out uart txd signal rxd dp int uart rxd signal tx2ul txd dp dm data[0] data[1] rxd txd rxd usb interface ulpi interface [+] feedback
cy7c68003 document number: 001-15775 rev. *i page 4 of 27 clocking tx2ul supports external crystal and clock inputs at the 13, 19.2, 24, and 26 mhz frequencies. the internal pll applies the proper clock multiply option depending on the input frequency. for appli- cations that use an external clock source to drive xi, the xo pin (in the 24-pin qfn package) is left floating. tx2ul has an on-chip oscillator circuit that us es an external 13, 19.2, 24, or 26 mhz (100 ppm) crystal with the following characteristics: parallel resonant fundamental mode 750 mw drive level 12 pf (5 percent tolerance) load capacitors 150 ppm tx2ul operates on one of two primary clock sources: lvcmos square wave clock input driven on the xi pin crystal generated sine wave clock on the xi and xo pins the selection between input clock source and frequency on the xi pin is determined by the chip configuration register loaded through the reset_n during confi guration mode. the external clock source requirements are shown in figure 3 on page 5. figure 2. crystal configuration power domains the tx2ul has three power supply domains: vcc vio vbatt tx2ul has two grounds: vss vssbatt vcc this is the core 1.8v power supply for the tx2ul. it can range anywhere from 1.7v to 1.9v during actual operation. vio this is the 1.8v to 3.3v multi range supply to the i/o ring. it can range anywhere from 1.7v to 3.6v during actual operation. vbatt this is the battery input supply that powers the 3.3v regulator block. it can range anywhere fr om 3.0 to 5.775v during actual operation. voltage regulator the internal 3.3v regulator block regulates the vbatt supply to the internal 3.3v supply for the usbio and xosc blocks. if the supply voltage at vbatt is below 3.3v, the regulator block switches the vbatt supply directly for the usbio and xosc blocks. power supply sequence tx2ul does not require a power supply sequence. all power supplies are independently sequenced without damaging the part. all supplies are up and stable for the device to function properly. the analog block contains circuitry that senses the power supply to determine when all supplies are valid. tx2ul xi xo pll 12 pf 12 pf xtal * 12 pf capacitor values assumes a trace capacitance of 3 pf per side on a four layer fr4 pca table 3. external clock requirements parameter description specification unit min max vn supply voltage noise at frequencies < 50 mhz 20 mv p-p pn_100 input phase noise at 100 hz 75 dbc/hz pn_1k input phase noise at 1 khz offset 104 dbc/hz pn_10k input phase noise at 10 khz offset 120 dbc/hz pn_100k input phase noise at 100 khz offset 128 dbc/hz pn_1m input phase noise at 1 mhz offset 130 dbc/hz duty cycle 30 70 % maximum frequency deviation 150 ppm [+] feedback
cy7c68003 document number: 001-15775 rev. *i page 5 of 27 operation modes there are six operation modes available in tx2ul. they are: normal operation mode configuration mode ulpi low power mode sleep mode carkit uart pass through mode tristate ulpi interface output mode (only available in 24-pin qfn package) when changing the operation modes, if the current and changing modes are not the normal operation mode, tx2ul first changes to the normal operation mode. for example, to change from ulpi low power mode to sleep mode, tx2ul changes to normal operation mode first, and then to sleep mode. the mode change state diagram in figure 3 shows the mode change path of tx2ul. the entries of the si x operations modes (20-pin csp package has five operation modes) are listed in table 4 and ta b l e 5 . there are three mode change transactions that require the reset_n assert or d eassert with tstate (see table 21 on page 21 for tstate). the three mode change transactions are: change from normal operation mode to configuration mode; reset_n is required to assert with tstate change from configuration mode to normal operation mode; reset_n is required to de-assert with tstate change from normal operation mode to sleep mode; reset_n is required to assert with tstate figure 3. mode change state diagram normal operation mode tri-state ulpi interface output mode (available in 24- pin qfn package only) sleep mode ulpi low power mode configuration mode carkit uart pass through mode table 4. tx2ul 20-pin cps package operation modes reset_n mode 0 (low) sleep mode 1 (high) normal operation mode 1 (high) enter into ulpi low power mode by setting suspendm register bit (in function control register) to 0 during the normal operation mode. 1 (high) enter into carkit uart pass through mode by setting carkit mode register bit (in interface control register) to 1 during the normal operation mode. 0 (low) when power on (vcc on) enter into configuration mode table 5. tx2ul 24-pin qfn package operation modes cs_n reset_n mode 0 (low) 0 (low) sleep mode 0 (low) 1 (high) normal operation mode 0 (low) 1 (high) enter into ulpi low power mode by setting suspendm register bit (in function control register) to 0 during the normal operation mode. 0 (low) 1 (high) enter into carkit uart pass through mode by setting carkit mode register bit (in interface control register) to 1 during the normal operation mode. 1 (high) 0 (low) configuration mode 1 (high) 1 (high) tristate ulpi interface output pins [+] feedback
cy7c68003 document number: 001-15775 rev. *i page 6 of 27 the operation and configuration modes are described in the sections operation modes on page 5 and configuration mode on page 16 respectively. the ulpi low power mode and sleep mode are described in the following sections. ulpi low power mode in this mode, the link optionally places the tx2ul in low power mode when the usb is suspended. tx2ul powers down all the circuitry except for the interface pins and full speed receiver. to enter low power mode, the link must set suspendm in the function control register to 0b. the tx2ul clock is stopped for a minimum of five cycles after tx 2ul accepts the register write. to exit low power mode, the link signals tx2ul to exit the mode by asynchronously asserting a signal, stp. the tx2ul wakes up its internal circuitry and when it meets the ulpi timing require- ments, it deasserts dir. the suspendm register is set to 1b. sleep mode sleep mode is entered by asserting reset_n during the normal operation mode. when reset_n is driven low for tstate (see table 21 on page 21 for tstate requirement) while cs_n is low, tx2ul enters sleep mode. vcc must remain supplied (on) during the sleep mode. this mode powers down all internal circuitry except the reset_n pi n and the chip_c onfig register. the ulpi interface bus is tristated. during the sleep mode ensure that: the ulpi interface i/os are either floating or driven high by the link dp and dm are either floating or pull to 0v deassert reset_n to exit the sleep mode. vid and pid the vid and pid are hard coded into product id and vendor id registers (read only) as shown in ta b l e 6 . table 6. immediate register values for vid and pid field name size (bit) address (6 bits) value rd wr set clr vendor id (vid) low 8 00h - - - b4h vendor id (vid) high 8 01h - - - 04h product id (pid) low 8 02h - - - 03h product id (pid) high 8 03h - - - 68h [+] feedback
cy7c68003 document number: 001-15775 rev. *i page 7 of 27 pinouts tx2ul is available in 20-ball wlcsp and 24-pin qfn package. the pin assignment is shown in figure 4 and figure 5 figure 4. pin assignment - tx2ul 20-ball wlcsp (top view) a5 vbatt a4 dm a3 dp b2 reset_n a2 xi c5 data[0] b5 vcc c3 data[6] b1 nxt c2 stp d5 data[1] d4 data[3] a1 vcc b3 vss c1 dir c4 data[2] b4 data[4] d3 data[5] d2 data[7] d1 clock a b c d 12345 table 7. pin definitions - tx2ul 20-ball wlcsp name ball no. type voltage description ulpi link interface data[0] c5 i/o 1.8v ulpi data to/from link data[1] d5 i/o 1.8v ulpi data to/from link data[2] c4 i/o 1.8v ulpi data to/from link data[3] d4 i/o 1.8v ulpi data to/from link data[4] b4 i/o 1.8v ulpi data to/from link data[5] d3 i/o 1.8v ulpi data to/from link data[6] c3 i/o 1.8v ulpi data to/from link data[7] d2 i/o 1.8v ulpi data to/from link clock d1 o 1.8v ulpi clock nxt b1 o 1.8v ulpi next signal stp c2 i 1.8v ulpi stop signal dir c1 o 1.8v ulpi direction usb dp a3 i/o usb usb d-plus signal dm a4 i/o usb usb d-minus signal miscellaneous reset_n b2 i 1.8v global reset. when reset_n is asserted during the vcc power on, tx2ul enters into configuration mode. duri ng normal operation mode, asserting reset_n resets the tx2ul and en ter into the po wer saving mode. xi a2 i 1.8v lvcmos single ended clock of frequency 13, 19.2, 24, or 26 mhz power and ground vcc b5, a1 power 1.8v low voltage supply for the digital core and i/o vbatt a5 power 3.0 - 5.775v high voltage supply for usb vss b3 gnd 0v common ground [+] feedback
cy7c68003 document number: 001-15775 rev. *i page 8 of 27 figure 5. pin assignment - tx2ul 24-pin qfn (top view) 1 6 2 3 4 5 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 data[0] data[1] data[2] data[3] data[4] data[5] data[6] data[7] clock dir stp dp dm vbatt xi xo vcc reset_n nxt vssbatt nc vcc vio cs_n 7 tx2ul vss (gnd) exposed die pad table 8. pin definitions - tx2ul 24-pin qfn name pin no. type voltage description ulpi link interface data[0] 4 i/o 1.8 - 3.3v ulpi data to/from link data[1] 5 i/o 1.8 - 3.3v ulpi data to/from link data[2] 6 i/o 1.8 - 3.3v ulpi data to/from link data[3] 8 i/o 1.8 - 3.3v ulpi data to/from link data[4] 9 i/o 1.8 - 3.3v ulpi data to/from link data[5] 11 i/o 1.8 - 3.3v ulpi data to/from link data[6] 12 i/o 1.8 - 3.3v ulpi data to/from link data[7] 13 i/o 1.8 - 3.3v ulpi data to/from link clock 14 o 1.8 - 3.3v ulpi clock nxt 17 o 1.8 - 3.3v ulpi next signal stp 16 i 1.8 - 3.3v ulpi stop signal dir 15 o 1.8 - 3.3v ulpi direction usb dp 22 i/o usb usb d-plus signal dm 23 i/o usb usb d-minus signal misc cs_n 7 i 1.8 - 3.3v when cs_n is de-asserted, all pins at ulpi interface are tri-stated reset_n 18 i 1.8 - 3.3v device chip global reset. w hen reset_n is asserted, tx2ul is in reset and enters into the power saving mode. xi 21 i 1.8v crystal or lvcmos single ended clock of frequency 13, 19.2, 24, or 26 mhz xo 20 o 1.8 - 3.3v crystal nc 2 - - no connect power and ground vcc 3, 19 power 1.8v low voltage supply for the digital core vio 10 power 1.8 - 3.3v power for multi-range i/os vbatt 24 power 3.0 - 5.775v high voltage supply for usb vssbatt 1 gnd 0 usb ground vss die paddle gnd 0 digital ground (core and i/o) [+] feedback
cy7c68003 document number: 001-15775 rev. *i page 9 of 27 synchronous operation modes this section describes the synchronous mo de of tx2ul ulpi interface protocol. ulpi transmit command byte (tx cmd) the link initiates transfers to tx2ul by send ing the transmit command byte as shown in ta b l e 9 . tx cmd byte consists of a 2-bit command code and a 6-bit payload. ulpi receive command byte (rx cmd) the receive command byte, as shown in table 10, is sent by tx2ul to update the link with linestate and usb receive information. the usb receive information includes linestate, rxactive, and rxe rror. after a usb transmit, tx2ul sends rx cmd with linestate indicating eop to the link. for high speed, eop is the squelch to squelch transition on linestate. figure 7 on page 10 shows how tx2ul sends rx cmd information to the link. the first packet show s a single rx cmd. if back to back changes are detected, tx2ul keeps dir asserted and sends back to back rx cmds as shown in the second packet. table 9. transmit command (tx cmd) byte format byte name command code data (7:6) command payload data (5:0) command description special 00b 000000b (noop) no operation. 00h is the idle value of the data bus. the link drives noop by default. xxxxxxb (rsvd) reserved command space. values other than those mentioned give undefined behavior. transmit 01b 000000b (nopid) transmit usb data that does not have a pid, such as chirp and resume signalling. the tx2ul starts transmitting on the usb beginning with the next byte. 00xxxxb (pid) transmit usb packet. data (3:0) indicates usb packet identifier pid (3:0) xxxxxxb (rsvd) reserved command space. values other than those mentioned give undefined behavior. regwrite 10b 101111b (extw) exte nded register write command. 8-bit address available in the next cycle. xxxxxxb (regw) register write co mmand with 6-bit immediate address. regread 11b 101111b (extr) exte nded register read command. 8-bit address available in the next cycle. xxxxxxb (regr) register read comm and with 6-bit immediate address. table 10. receive command (rx cmd) byte format data name description and value 1:0 linestate ulpi linestate signals. data[0] = linestate (0) data[1] = linestate (1) 3:2 reserved 5:4 rxevent encoded utmi event signals value rxactive rxerror 00 0 0 01 1 0 11 1 1 10 x x 7:6 reserved [+] feedback
cy7c68003 document number: 001-15775 rev. *i page 10 of 27 figure 6. sending rx cmd usb data transmit (nopid) in this mode, the link transmits data on the usb without a packet identifier (pid) by sending a tx cmd byte of the nopid type. tx2ul asserts nxt (see figure 8 on page 11 ) in the first cycle of tx cmd and deasserts nxt when it detects stp to be high. because this command does not contain pid data, tx2ul waits for the next data byte before beginning transmission on the usb. when the last byte is transferred by the tx2ul, th e link asserts stp for one cycle and drives da ta to 00h if no transmit errors occur. t he link does not assert stp before the first byte is transferred by the tx2ul. figure 7. usb data transmit (nopid) clock data[7:0] dir stp nxt turn around rx cmd turn around turn around rx cmd rx cmd turn around d1 clock data[7:0] dir stp nxt d0 tx cmd (nopid) d2 [+] feedback
cy7c68003 document number: 001-15775 rev. *i page 11 of 27 usb data transmit (pid) in this mode, the link transmits data on the usb with a packet id entifier (pid). the li nk first drives a tx cmd byte as illustr ated in figure 9 on page 11 to transmit a usb packet. the link sets the command code to 01b (transmit) and places the usb packet identifier (pid) on data[3:0] (see table 9 on page 9) . tx2ul throttles the data using nxt such that the link provi des the next byte in the cycle after nxt is detected as high. figure 8. usb data transmit (pid) usb packet receive as shown in figure 10 on page 12, when tx2ul receives the usb data it gains ownership of the data bus by asserting dir. the dir is previously either high or low. if dir is low (see figure 9 ), tx2ul asserts both dir and nxt so that the link knows immediately that this is a usb receive packet. if dir is high (see figure 10 on page 12 ), tx2ul deasserts nxt and drives an rx cmd with the rxevent field set to the rxactive state. the tx2ul starts driving data in the following cycle or output s rx cmd until usb data is avail able. valid usb packet data is presented to the link by asserting nxt and placing a byte on the bus. when nxt is low, tx2ul drives th e rx cmd byte. all rx cmd changes during the usb packet receiv e are signaled when nxt is low. if nxt is never low during the packet receive, all rx cmd changes are repl aced with a single rx cmd update. this updat e is sent at the end of the usb packet receive, when the ulpi bus is available. the rx cmd update always conveys the curren t rx cmd values and not the previous one. figure 9. usb receive while dir is previously low clock data[7:0] dir stp nxt d1 tx cmd (pid) d2 d3 clock data[7:0] dir stp nxt turn around rx cmd pid d1 rx cmd d2 d3 turn around [+] feedback
cy7c68003 document number: 001-15775 rev. *i page 12 of 27 figure 10. usb receive while dir is previously high immediate register read and write an immediate register is accessed by sending the tx cmd byte first (see figure 11 and figure 12 on page 13 ). this byte is sent as a regread or regwrite command, depending on the intended operation. for a register write (see figure 11 ), the link first sends a register write tx cmd by te and waits for nxt to assert. after nxt asserts, the link sends the register write data and waits for nxt to asse rt again. after the second assertion is detected, the link asse rts stp in the following cycle to complete the operation. the tx2ul detec ts this stp assertion before it can accept another transmit co mmand. if the tx2ul aborts rewrite by asserti ng dir, the link repeats the entire process again when the bus is idle. for a register read (see figure 12 on page 13 ), the link sends a register read command and waits for nxt to assert. in the cycle after nxt asserts, the tx2ul asserts dir to gain control of the data bus. in the cycle, after dir asse rts the tx2ul returns the regis ter read data. the tx2ul does not assert nxt when dir is asserted du ring the register read operation, even during the cycle when th e register read data is returned. if the tx2ul aborts the regread by asserting dir earlier than shown in figure 12 on page 13 , the link retries the regread when the bus is idle. figure 11. register write clock data[7:0] dir stp nxt rx cmd pid previous rx cmd (rxactive) d1 rx cmd d2 d3 turn around clock data[7:0] dir stp nxt data tx cmd (regwrite) [+] feedback
cy7c68003 document number: 001-15775 rev. *i page 13 of 27 figure 12. register read immediate register read and write aborted by usb receive a register read is the only instance where ulpi does not use nx t to acquire data. the nxt signal is asserted only during usb re ceive to distinguish this type of receive from other types of data transfers. register read and write operatio ns are aborted when the tx2ul sends a rx cmd, except during the cycle where register read data is returned to the link. tx2ul asserts both dir and nxt whenever a register read or wr ite is aborted by a usb receive during the initial transmit comman d byte or in the same cycle that the register read data returned to the link. figure 13. register read or write aborted by usb receive during tx cmd byte clock data[7:0] dir stp nxt turn around tx cmd (regread) data turn around clock data[7:0] dir stp nxt regread or regwrite usb receive tx cmd (reg) turn around rx cmd pid d1 d2 d3 [+] feedback
cy7c68003 document number: 001-15775 rev. *i page 14 of 27 back to back immediate register read and write and usb receive when a usb receive occurs in the same cycl e that the register read data is returned to the link, the tx2u l first returns the re gister read data, not a rx cmd byte (see figure 14 ). when a usb receive occurs in the cycle immediately after a re gister read completes, the tx2ul places the usb receive data back-to-back with the register read (see figure 15 ). the link accepts back-to-back packets where dir does not deassert between packets. if dir asserts during the same cycle that stp is asserted at the end of a regi ster write, then the tx2ul considers the register write to have successfully executed (see figure 16 on page 15 ). when a usb receive starts in the cycle after the register read data is returned to t he link, it results in two cycles of bus tu rnaround when dir deasserts for a single cycle (see figure 17 on page 15 ). figure 14. usb receive in same cycle as register read data. usb receive is delayed figure 15. register read follow ed immediately by a usb receive clock data[7:0] dir stp nxt regread usb receive turn around tx cmd (regreg) reg data rx cmd (rxactive) pid d1 d2 turn around tx cmd (regreg) reg data rx cmd (rxactive) pid d1 d2 clock data[7:0] dir stp nxt regread usb receive [+] feedback
cy7c68003 document number: 001-15775 rev. *i page 15 of 27 figure 16. register write followed immedi ately by a usb receive during stp assertion figure 17. register read followed by a usb receive clock data[7:0] dir stp nxt regwrite usb receive turn around tx cmd (regreg) data rx cmd (rxactive) pid d1 d2 turn around tx cmd (regreg) reg data pid d1 clock data[7:0] dir stp nxt regread usb receive turn around turn around [+] feedback
cy7c68003 document number: 001-15775 rev. *i page 16 of 27 configuration mode tx2ul is configured in the input clock type and frequency for the xi and xo in configuration mode. the 20-pin csp package and 24-pin qfn package have different procedures to enter the configuration mode. configuration mode in 20-pin csp package to enter the configuration m ode keep the reset_n low during vcc power on for tstate (see figure 19 on page 22 for the timing diagraming and table 21 on page 21 for the tstate timing requirement). when tx2ul enters the configuration mode, the peripheral controller (link devic e) generates the pulses (falling edge) at the reset_n pin to configure tx2ul. tx2ul configures its internal oscillat or base on number of received pulses at the reset_n pin. when the configuration is completed, deassert reset_n (high) for tstate to exit the configuration. if the tx2ul nee ds to enter the configuration mode again, it must go through the following power cycle: vcc off ? reset_n low ? vcc on. configuration mode in 24-pin qfn package to enter the configuration mode keep the reset_n pin pulled low for tstate (see figure 20 on page 22 for the timing diagraming and table 21 on page 21 for the tstate timing requirement) while deasserting cs_n (high). when tx2ul enters the configuration mode, th e peripheral controller (link device) generates the pulses (f alling edge) at the reset_n pin to configure tx2ul. tx2ul configures its internal oscillator base on number of received pulses at the reset_n pin. when the configuration is completed, assert the cs_n (low) for tstate (see figure 21 on page 21 for the timing) to ex it the configuration mode. figure 19 on page 22 shows the timing diagram of entering and exiting the configur ation mode. the configuration options are listed in table 11 . the tx2ul is defaulted to 26 mhz with single end clock input (to xi). power on reset (por) tx2ul has an internal power on reset (por) block that provides power on reset and power management control functionality. this por function complies with all the parameters required by the ulpi specification. register tx2ul provides an immediate regist er set that is defined by the ulpi specification for control and configuration functions. register map the ulpi specifications define an immediate register set with a 6-bit address that forms a part of the transmit command byte,as shown in shown in table 12 . table 11. tx2ul configuration options number of pulses at reset_n pin during configuration mode configuration description 0 pulses 26 mhz clock input on xi (default) 1 pulses 19.2 mhz clock input on xi 2 pulses 24.0 mhz clock input on xi 3 pulses 13.0 mhz clock input on xi 4 pulses 26 mhz crystal on xi/xo 5 pulses 19.2 mhz crystal on xi/xo 6 pulses 24.0 mhz crystal on xi/xo 7 pulses 13.0 mhz crystal on xi/xo table 12. register map field name size (bits) address (6bits) rd wr set clr immediate register set vendor id low 8 00h - - - vendor id high 8 01h - - - product id low 8 02h - - - product id high 8 03h - - - function control 8 04-06h 04h 05h 06h interface control 8 07-09h 07h 08h 09h debug 8 15h - - - scratch register 8 16-18h 16h 17h 18h carkit control (optional) 8 19-1bh 19h 1ah 1bh vendor specific register set drive strength and slew rate 8 31h 31h - - usb interface control register 8 35h 35h - - [+] feedback
cy7c68003 document number: 001-15775 rev. *i page 17 of 27 ta b l e 1 3 to table 17 on page 18 define the read, write, set, and clear regi ster options. the following are the conventions: rd or rd = read wr or wr = write set or s = set clr or c = clear immediate register set the details of all immediate registers of tx2ul are shown in table 6 on page 6, table 18 on page 19 , and table 20 on page 21 . function control register control ulpi function setting of tx2ul table 13. function control register (address: 04h - 06h [read], 04h [write], 05h [set], 06h [clear]) bit field name description access reset value 1:0 xcvrselect selects the re quired transceiver speed. 00b: enable hs transceiver 01b: enable fs transceiver 10b: reserved 11b: enable fs transceiver for ls packets. rd/wr/s/c 01b 2 termselect controls the internal 1.5k pull up resistor and 45 hs terminations. rd/wr/s/c 0b 4:3 opmode selects the required bit encording style during transmit. 00b: normal operation 01b: non-driving 10b: disable bit stuff and nrzi encoding 11b: do not automatically add syn c and eop when transmitting. it is used only for hs packets. rd/wr/s/c 00b 5 reset active high transceiver reset. af ter the link sets this bit, tx2ul asserts dir and resets ulpi core. when the reset is completed, dir is de-asserted and automatic ally clears this bit. after de-asserting dir, tx2ul re-asserts dir and sends and rx cmd update to the link. the link waits for dir to de-assert before using ulpi bus. it does not reset the ulpi interface or ulpi register set. rd/wr/s/c 0b 6 suspendm active low. put tx2ul into low power mode. tx2ul powers down all blocks except the full speed receiver and ulpi interface pins. tx2ul sets this bit to ??1?? when exits from low power mode. 0b: enter into low power mode 1b: normal operation mode rd/wr/s/c 1b 7 reserved rd x [+] feedback
cy7c68003 document number: 001-15775 rev. *i page 18 of 27 interface control register this register enables alternativ e interface and tx2ul features. debug register this register indicates the current val ue of various signals useful for debugging. scratch register this register is for testing purpose only. the lin k can read, write, set and clear this register. carkit control register this register controls the txd and rxd in carkit uart pass through mode. it has no co ntrol function if the carkitmode bit in in terface control register is not set. table 14. interface control register (address: 07h - 09h [read], 07h [write], 08h [set], 09h [clear]) bit field name description access reset value 1:0 reserved rd xxb 2 carkitmode changes the ulpi interface to carkit interface that support uart pass through mode. this bit is cleared when it exits from carkit uart pass through mode. 0b: disable serial carkit mode 1b: enable serial carkit mode rd/wr/s/c 0b 6:3 reserved rd xxxxb 7 interface protect disable controls circuitry built into tx2ul for protecting the ulpi interface when the link tristates stp and data[7:0]. any pull ups or pull downs employed by this feature are disabled 0b: enable the interface protect circuit 1b: disable the interface protect circuit rd/wr/s/c 0b table 15. debug register (address: 15h [read only]) bit field name description access reset value 0 linestate0 contains the current value of linestate(0) rd 0b 1 linestate1 contains the current value of linestate(1) rd 0b 7:2 reserved rd 000000b table 16. scratch register (address: 16h - 18h [read], 16h [write], 17h [set], 18h [clear]) bit field name description access reset value 7:0 scratch empty register byte for testing pur poses. the link software reads, writes, sets, and clears this register. rd/wr/s/c 00000000b table 17. carkit control register (address: 19h - 1bh [read], 19h [write], 1ah [set], 1bh [clear]) bit field name description access reset value 1:0 reserved rd xxb 2 txden routes txd signal from data[0] pin to dm pin rd/wr/s/c 0b 3 rxden routes rxd signal from dp pin to data[1] pin rd/wr/s/c 0b 7:4 reserved rd xxxxb [+] feedback
cy7c68003 document number: 001-15775 rev. *i page 19 of 27 drive strength and slew rate configuration register this register is mapped to the ve ndor specific registers address. this register configures the drive strength and slew rate of the outputs. usb interface control register this register is mapped to the vendor specific registers address. this register enables or disables the usb interface. table 18. drive strength and slew rate configuration register (address: 31h [read], 31h [write]) bit field name description access reset value 1:0 drivestrength configure the drive strength on the output pins 00b: full drive strength 01b: three quarter drive strength 10b: half drive strength 11b: quarter drive strength rd/wr 00b 2 slewrate configure the slew rate on the output pins 0b: slow slew rate 1b: fast slew rate rd/wr 0b 7:3 reserved rd 00000b table 19. usb interface control regist er (address: 35h [read], 35h [write]) bit field name description access reset value 1:0 reserved when write to this register, this field must be filled in 0s rd 00b 2 usbenable usb interface control 0b: disable usb interface 1b: enable usb interface rd/wr 0b 7:3 reserved when write to this register, this field must be filled in 0s rd 00000b [+] feedback
cy7c68003 document number: 001-15775 rev. *i page 20 of 27 absolute maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature .................................... 65 c to +150 c ambient temperature with power supplied (industrial) ............................ 40 c to +85 c supply voltage to ground potential vcc ..................................................................0.5v to +2.0v vio ...................................................................0.5v to +4.0v vbatt ..........................................................0.5v to +5.775v dc input voltage to any input pin ....................1.89v to 3.6v depends on i/o supply voltage. inputs are not over voltage tolerant. dc voltage applied to outputs in high z state ........... ................. 0.5v to vcc+0.5v static discharge voltage (esd) from jesd22-a114> 2000 v latch up current .................................................... > 200 ma maximum output short circuit current for all i/o configurations. (vou t = 0v)........................ 100 ma operating conditions t a (ambient temperature under bias) industrial ......................................................... 40 c to +85 c vcc supply voltage ...........................................1.7v to 1.9v vio supply voltage ............................................1.7v to 3.6v vbatt supply voltage ...................................3.0v to 5.775v [+] feedback
cy7c68003 document number: 001-15775 rev. *i page 21 of 27 dc characteristics ac characteristics table 20. dc specifications for all voltage supplies parameter description conditions min typ max unit vcc core voltage supply 1.7 1.8 1.9 v vio ulpi interface i/o voltage supply (this i/o supply is not available on 20-ball wlcsp package) 1.7 1.8, 2.5, 3.3 3.6 v vbatt crystal voltage supply 3.0 5.775 v v por(trip) power on reset trip voltage 1.0 1.5 v v ih1 input high voltage 1 all ports except usb, 2.0v < vio < 3.6v 0.625*vio vio + 0.3 v v ih2 input high voltage 2 all ports except usb, 1.7v < vio < 2.0v vio? 0.4 vio + 0.3 v v il input low voltage 0.3 0.25*vio v v oh output high voltage i oh (max) = 0.1 ma 0.9*vio v v ol output low voltage i ol (min) = 0.1 ma 0.1*vio v i ix input leakage current all i/o signals held at vddq 1 1 a i oz output leakage current all i/o signals held at vddq 1 1 a icc supply current continuous receive 30 65 ma continuous transmit 30 65 ma ulpi low power mode (suspend) vcc = 1.8 v 300 750 a sleep mode - ulpi interface bus is either hz or drive high - dp and dm must be hz or pull low 540 a i pu pull up current interface protect enabled; stp pin only; v i = 0v -13 -80 a i pd pull down current interface protect enabled; data[7:0] only; v i = vio 16 90 a table 21. ulpi timing parameters parameter description min max unit tcs setup time for control input 5.8 ns tds setup time for data input 5.8 ns tch hold time for control input 0 ns tdh hold time for data input 0 ns tcd output delay time for control output 7.6 9.0 ns tdd output delay time for data output 7.6 9.0 ns tstate mode state change time 500 s tpw pulse width 200 10000 ns [+] feedback
cy7c68003 document number: 001-15775 rev. *i page 22 of 27 figure 18. ulpi timing diagram figure 19. 20-pin csp package configuration mode entry timing diagram figure 20. 24-pin qfn package configuration mode entry timing diagram clock control in (stp) data[7:0] in tcs tch control out (dir, nxt) tds tdh tcd tcd data [7:0] out tdd tdd vcc reset_n normal operation mode tstate configuration mode entering into configuration mode tstate exiting from configuration mode configuration pulses (falling edge) tpw tpw tpw vcc cs_n reset_n normal operation mode tstate configuration mode entering into configuration mode tstate exiting from configuration mode configuration pulses (falling edge) tpw tpw [+] feedback
cy7c68003 document number: 001-15775 rev. *i page 23 of 27 figure 22. connecting 20-ball wlcsp package tx2ul with a standard peripheral controller with external clock figure 21. ac test loads and waveforms data[0] data[1] data[2] data[3] data[4] data[5] data[6] data[7] data[0] data[1] data[2] data[3] data[4] data[5] data[6] data[7] clock clock dir nxt stp reset_n vss dm dp dm dp dir nxt stp reset_n vbatt vcc 1.8v 3.3 ? 5.775v 2 3 4 usb connector b3 a5 c5 d5 c4 a4 d4 b4 a3 c3 a1 d3 b2 b1 d2 a2 c2 c1 d1 xi 13/19.2/24/26 mhz external clock tx2ul csp package peripheral controller b5 [+] feedback
cy7c68003 document number: 001-15775 rev. *i page 24 of 27 ordering information package diagram figure 23. 20-pin wlcsp package outline ordering code package type support clock input frequencies (mhz) CY7C68003-20FNXI 20-ball wlcsp 13, 19.2, 24, 26 cy7c68003-24lqxi 24-pin qfn 13, 19.2, 24, 26 cy7c68003-24lqxit 24-pin qfn tape and reel 13, 19.2, 24, 26 001-13856 *b [+] feedback
cy7c68003 document number: 001-15775 rev. *i page 25 of 27 figure 24. 24-pin qfn package outline 001-13937 *c [+] feedback
cy7c68003 document number: 001-15775 rev. *i page 26 of 27 document history page document title: cy7c68003 mobl-usb ? tx2ul usb 2.0 ulpi transceiver document number: 001-15775 revision ecn orig. of change submission date description of change ** 1094246 vso, xva see ecn initial release *a 1188703 vso see ecn update the tstate min requirement (from 200 us to 500us) in table 21 section sleep mode add (see table 21 for tstate requirement) section of operating conditions (page 19), the second vcc corrected to vio. table 19, the reference voltage for the v ih1 , v ih2 , v il , v oh , and v ol has corrected from vcc to vio. *b 1505863 vso/aesa see ecn change in ordering information. *c 2081867 vso/aesa see ecn update the esd description in the features list. updated the descripti on of section ?? power supply sequence?? updated the section of chip section (cs_n) updated the section of operat ion modes - tri-state mode only available in 24-pin qfn package updated figure 3. added table 4. updated figure 4 and table 7 (csp pin assignment has been changed) updated the section of configuration mode correct the hyper link section of immediate register set correct the word of ??reserved?? in table 14 updated ulpi timing parameters table (table-21) updated ulpi timing diagram (figure 18) added figure 19. removed usb interface control register section and table in page 19 updated figure 22. *d 2552066 vso 08/13/2008 in the first page, feature list, update the csp dimension from ??2.2 x 1.8 mm?? to ??2.14 x 1.76 mm??. updated table 12 add usb interface control register section *e 2597682 vso/aesa 10/28/2008 removed prelim inary in master pages (turn into final data sheet). updated data sheet template. updated ordering information table. in the clocking section, added a bullet ??150 ppm???. table 3: ? changed pn_dc to pn_100 ? changed dc to 100 ? change the unit of db to dbc/hz ? added a row of ??maximum frequency devia- tion?? *f 2671871 vso/pyrs 03/13/2009 updated suspend current in table 20 (clarified vcc = 1.8v). changed all tx3, tx3lp18 to tx2ul *g 2765711 tik/radh 09/18/2009 posting to external web. *h 2920278 vso/aesa 04/21/2010 added ?suport usb device mode only? in the feature section. added table of conetnts. updated links in sales, solutions, and legal information. [+] feedback
document number: 001-15775 rev. *i revised september 22, 2010 page 27 of 27 mobl-usb is a trademark of cypress semiconductor. all other products and company names mentioned in this document may be the tr ademarks of their respective holders. cy7c68003 ? cypress semiconductor corporation, 2007-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress??? pr oduct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 *i 3035786 hbm 09/22/2010 post to external web. document history page (continued) document title: cy7c68003 mobl-usb ? tx2ul usb 2.0 ulpi transceiver document number: 001-15775 revision ecn orig. of change submi ssion date description of change [+] feedback

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